Semiconductor devices such as microprocessors can be made up of millions of transistors, each interconnected by thin metallic lines branching over several levels and isolated electrically from each other by layers of dielectric materials. When a new semiconductor design is first produced in a semiconductor fabrication facility, it is typical to find that the design does not operate exactly as expected. It is then necessary for the engineers who designed the device to test their design and “rewire” it to achieve the desired functionality. Due to the complexity of building a semiconductor device in the semiconductor fabrication facility, it typically takes weeks or months to have the re-designed device produced. Further, the changes implemented frequently do not solve the problem or expose a yet further difficulty in the design. The process of testing, re-designing and re-fabrication can significantly lengthen the time to market new semiconductor devices.
Circuit editing—the process of modifying a circuit during its development without having to remanufacture the whole circuit—provides tremendous economic benefits by reducing both processing costs and development cycle times. In most cases, the feature to be modified is buried under other material, such as insulating layers, and, in the case of “flip chips,” semiconductor layers. Therefore it is typically necessary to mill down through these layers of materials to reach the metal feature of interest without damaging adjacent circuit features. Once the feature is exposed, circuit editing normally requires that the feature of interest either be cut to break an electrical connection or electrically connected to other features by ion beam assisted deposition of conducting “straps.”
Over the past decade, techniques have been developed to allow Focused Ion Beam (FIB) systems to reduce the time required for this procedure of perfecting a design. FIB systems produce a narrow, focused beam of charged particles (hereinafter referred to as ions) which is typically scanned across a specimen in a raster fashion, similar to a cathode ray tube. In most commercial FIB systems, the ions used are positively charged gallium ions (Ga+) from liquid metal ion sources. Modem FIB systems can be used to form an image of a sample surface much like an electron microscope. The intensity at each point of the image is determined by the current of secondary electrons or other particles ejected by the ion beam at the corresponding point on the substrate. The ion beam can also be used to remove material from the sample surface or to deposit material (typically by using a gas that decomposes in the presence of the ion beam and deposits material onto the surface.). When used to remove material, the heavy gallium ions in the focused ion beam physically eject atoms or molecules from the surface by sputtering, that is, by a transfer of momentum from the incoming ions to the atoms at the surface.
FIB instruments were first used to “cut” metal lines, typically comprised of alloys of aluminum and/or tungsten, on prototype devices, thus allowing for design verification in simple cases. Both aluminum and tungsten can be milled by rastering a beam of gallium ions across the area of interest. The beam is typically scanned across the area to be milled using digital electronics that step the beam from point to point. The distance between points is referred to as the pixel spacing. Pixel spacing is typically less than the beam spot size, that is, each subsequent beam position overlaps the previous position to ensure a uniform cut and a smooth finish. This method is referred to as ‘Default Milling’. Milling methods have been well documented, for example, in U.S. Pat. No. 5,188,705 to Swanson, et. al. for “Method of Semiconductor Device Manufacture”.
Chemistries have also been developed that selectively attack aluminum, causing it to sputter much more quickly in the presence of certain gases than with just the ion beam alone. This process is well-known within the art and is commonly referred to as Gas Assisted Etching (GAE). Because it speeds up the removal process, GAE can be used, for example, to mill relatively large areas of a surface layer or layers to expose underlying layers for observation and testing. Further, techniques have been developed using special gas chemistries in the FIB system to permit selective deposition of thin metallic lines to connect two or more conductors, selective removal of dielectric insulators but not metallic interconnects, and selective removal of metal interconnects without removing the dielectric insulators. Essentially, these capabilities now permit prototyping and design verification in a matter of days or hours rather than weeks or months as re-fabrication would require.
Until recently, the typical metals used for metallic interconnects were primarily alloys of aluminum and/or tungsten. Traditionally, the circuit pattern was formed on a semiconductor chip by a photolithographic process which includes depositing one or more metallization layers (such as an aluminum alloy film) and etching the desired pattern into each metallization layer. The above described advances in FIB system techniques for cutting and depositing metal interconnects were specifically designed for these metal alloys and their particular physical characteristics.
In recent years, semiconductor manufacturers have begun a migration toward the use of copper as a replacement for aluminum interconnects. As manufacturers strive to increase the speed at which chips work, the use of copper interconnects provides several advantages over aluminum. For example, copper has lower sheet resistance and exhibits both improved metal line and line/via/line electromigration reliability.
Although the advantages of copper over aluminum have been known for some time, copper is very difficult to etch. As a result, it is impractical to manufacture copper interconnects using the typical process of depositing a metallization layer and then etching the desired pattern. Instead, copper wiring is typically patterned using a single or dual damascene process that reverses conventional metallization. Rather than depositing dielectric into spaces etched in metal, a damascene process cuts lines into the dielectric, fills them with metal, then polishes the excess metal away using a process known as chemical mechanical polishing (CMP).
CMP typically makes use of an abrasive slurry and one or more polishing pads to remove excess material and achieve global planarization of a wafer surface. However, determining the exact end point for the CMP process can be difficult. A main reason for this is that different materials polish at different rates. Copper is much softer than typical dielectric materials such as SiO2, and as a result it polishes away more quickly. Copper lines and pads tend to “dish” or be overpolished in the center. Further, thin or isolated features tend to polish more rapidly than dense features since the entire force of the polishing pad is directed at a smaller area. Erosion occurs when narrow arrays of copper and dielectric polish more quickly than non-patterned areas.
Both dishing and erosion can thin the metal wiring and thus increase the sheet resistance of the metal wiring. Further, the increase in sheet resistance is not constant. The sheet resistance may increase by tens of percentage points depending on the circumstances and the layout of the metal wiring. Erosion can result in a sub-planar dip on the wafer surface. When the subsequent layer of interconnect is completed, a shallow “pool” of copper can fill this dip, causing short-circuits between adjacent wires.
One way to reduce dishing and erosion is the use of dummy features to create a uniform pattern density across the entire wafer surface. For example, wherever the distance between any active features in a wiring layer is greater than a certain minimum width, dummy copper pads can be formed in the dielectric so that the entire wafer surface will polish at a uniform rate. The placement of this type of dummy feature is referred to as “tiling” because the dummy features look like tiles when viewed from above. Ideally, the use of dummy copper pads or tiles keeps the relative percentage of copper to dielectric constant over the entire wafer surface.
A problem arises, however, when one or more layers containing dummy copper pads and dielectric must be removed to allow circuit editing of active features on a lower layer. The same types of difficulties that make it difficult to etch copper to form circuit wires also make it difficult to remove relatively large areas of dummy copper and dielectric. FIB sputtering of copper is much more difficult than sputtering aluminum alloys. Aluminum atoms have a lower atomic mass and less “stopping power” than copper atoms. As a result, simple ion beam milling of the copper atoms is less effective than the equivalent milling of aluminum. Further, a gas chemistry that permits GAE of copper has not yet been successfully developed. The halogens that are used to enhance focused ion beam etching of other metal interconnect materials do not significantly enhance the etching of copper, and no other chemical suitable for routine FIB milling of copper has been found. The etch byproducts formed during the use of halogen compounds on copper at room temperature have low volatility and tend to leave detrimental deposits on the sample surface and via side walls.
Moreover, the milling of copper without chemicals has been found to produce non-uniform material removal, even when the ion beam is applied uniformly. This non-uniform milling is thought to be attributable to a number of factors, including the formation of etch-resistant copper regions and differences in the crystallographic orientation within the copper layer being milled. The non-uniform copper removal causes the floor of the etched area to become non-planar, which in-turn can cause unacceptable milling of the material under the copper conductor; i.e., as milling continues to remove the remaining copper from one region under the ion beam, significant damage is incurred by milling the exposed underlayer in areas where the copper has already been removed.
These problems are exacerbated when layers comprising both copper and dielectric need to be removed. For example, during circuit editing it is common to have to clear a relatively large area of multiple layers, each layer having copper and dielectric materials embedded in the same layer. When these types of mixed layers are sputtered by a FIB, the difference in sputtering rate between copper and the dielectric material also tends to result in a non-uniform milling floor.
All of these problems tend to worsen as multiple layers are removed. As many as eight such layers are common for modern semiconductor design. Usually, after only two or three layers, copper from different levels is being exposed and milled simultaneously. This makes FIB circuit edits of circuitry buried underneath a large number of mixed copper and dielectric layers very challenging.
Although several techniques to improve the uniformity of copper milling are known, as discussed in greater detail below, none of these techniques adequately solve the problems of milling through mixed copper and dielectric layers. Hence, there is a need for an improved technique to allow more uniform milling through multiple layers of mixed copper and dielectric.